CPU Performance Architect
Huawei Canada’s Research Center excels in general processing as well as telecom and cloud network infrastructure, including 4G, 5G, optical, microwave, switch/router technology, high-speed SerDes, ARM processors, and fully custom network processors.
Huawei’s processor architecture team is seeking CPU Performance Architects to join our team and contribute to the microarchitecture of next generation, high performance, highly efficient, low power ARM cores.
What you’ll do:
As a member of the Microarchitecture Modeling and Optimization team you will be responsible for implementation of simulators and models of leading edge ARM cores for use in SOC devices for several different markets.
Our current architects perform a wide range of duties, including:
- Researching & modeling complex microarchitectural alternatives in order to select new microarchitectures and improve existing microarchitectures.
- Researching industry benchmarks and related software in order to identify how microarchitectureal decisions impact performance, power, and area.
- Working with microarchitects and implementation teams to ensure the successful delivery of an ARM core which meets prescribed performance, power, and area targets.
What you should have:
- BS, MS, or PhD in Electrical or Computer Engineering, Computer Science, or related field with experience in CPU microarchitecture and performance modeling.
- Working knowledge of:
- Modern CPU microarchitecture and instruction sets
- CPU cache structures and algorithms
- Branch prediction algorithms
- ARM ISA, microarchitecture, and system design considered a strong asset.
- Strong experience with C++ is a must have. EDA languages such as System Verilog is a strong asset
- gem5 or equivalent microarchitecture simulators operating at various abstraction levels.
- Scripting languages such as Python, etc.
- Queuing theory, complex arbitration, and flow control.
- Real-time embedded programming, deadlocks, and race conditions.
- Implementing complex algorithms in hardware.
- ASIC design, verification, and PD challenges, and how architectural decisions influence these activities.